GRAPH PARALLELISM
Massively parallel edge intersection strategies for high-speed triangle enumeration.
Research Dossier / 03
Scalable Triangle Counting in Massive Graphs using GPU Acceleration
Research on high-performance triangle counting algorithms for large-scale sparse and dense graphs using GPU-accelerated parallel architectures.
Short LabelGPU Triangles
- Institution
- Research under Dr. Vishwesh Jatala, IIT Bhilai
- Role
- Researcher
- Active Period
- 2024 - Present
CUDA
Graph Processing
Parallel Algorithms
Sparse Matrices
Method + Iterations
Step 01
Implemented parallel intersection-based triangle counting using CUDA thread-level optimizations.
Step 02
Optimized adjacency list traversal with memory coalescing techniques.
Step 03
Reduced redundant computations using degree-based node ordering heuristics.
Step 04
Introduced dynamic load balancing for high-degree node partitions.
Step 05
Built profiling scripts for occupancy, memory throughput, and branch efficiency analysis.
Step 06
Benchmarked scalability across increasing graph sizes and compared with CPU-based baselines.
Visual Notes
SPARSE MATRIX VIEW
Sparse adjacency representations and ordered intersections for efficient triangle discovery.
SCALING CURVES
Profiling and benchmark snapshots across graph sizes, highlighting GPU acceleration characteristics.